While a dynamic random access memory has heretofore been provided for improving integration complexity at a speed larger by a factor of four in three years, the volume demand for the memory has increased more and more in keeping with the explosive sales of personal computers in recent years. Mass production facilities for devices of 16 M bits are almost in the final stage of operation and, furthermore, development toward mass production of devices of 64 M bits, which uses a linewidth of 0.35 .mu.m, is currently being advanced, said linewidth being a key element in a technology of miniaturization to be employed in the next generation of memory devices.
To achieve a memory cell on a smaller scale, a three dimensional structure of a capacitor has been adopted in generations after the fourth generation in order to secure a larger capacitance in a smaller area. In employment of this structure of a capacitor, however, the height of a capacitor has been on the increase in every generation, since the magnitude of the required charge capacity has almost not, changed through the generations. As a result, in the case where a COB cell (COB is an abbreviation for Capacitor Over Bitline) in which a capacitor is formed above a dataline is employed, a high topological difference is produced between a memory cell region and a peripheral circuit region.
In more detail, for example, in the case of 1 G bits, which is a generation following the next generation, the height of a capacitor is about 1 .mu.m, provided that a tantalum oxide film (which is equivalent to a silicon oxide film of a thickness of 3.3 nm) as a capacitor insulating film is used and a cylindrical capacitor is adopted. In the presence of a topological difference of such a magnitude between a memory cell array and a peripheral circuit region, the following steps in the formation of the metal interconnection have experienced much difficulty, that is, the steps of photolithography and dry etching could not be properly performed. In the photolithography step, since resolution and depth of focus are inversely proportional to each other, the depth of focus becomes smaller as the resolution is increased in order to achieve a finer pattern. Therefore, if a high topological difference is present, poor resolution results, thereby to adversely affect the patterning. On the other hand, in the dry etching step, if a high topological difference is present, there also arises problems that a film is partly left unetched or the resulting pattern is misshaped relative to its intended configuration.
As a means to solve such problems, there has been proposed a method in which, as shown in FIG. 2, an Si substrate is prepared in such a way that an intentional topological difference is provided on the substrate and the topological difference is adjusted so that a region of the surface on which the memory array is formed is lower in height than another region of the surface on which the peripheral circuit is formed, whereby the topological difference between a memory array region and a peripheral circuit region is reduced (see Laid-Open Japanese patent application 63-266866). However, it is difficult to apply this technique to a DRAM of 1 G bits class which requires a minimum process size of 0.15 .mu.m. The following are the reasons for such difficulty.
In the technique disclosed in a publication of Laid-Open Japanese patent application 63-266866, a semiconductor substrate (or wafer) as a starting material is prepared with a topological difference, and therefore the height of the surface of a device isolation region is not uniform thereacross, that is, the height is different between a memory array region and the peripheral circuit region. Conventionally there has been generally adopted a technique in which an oxide film is selectively formed (this is called LOCOS: Local Oxidation of Silicon), and such a device isolation region has been formed in a wafer with a high step by this technique. In a 1 G bits DRAM, however, the required size for device isolation is 0.15 .mu.m. A LOCOS technique cannot be, in such a condition, applied to a 1 G bits DRAM in order to electrically isolate elements, and so it has been considered that a shallow trench isolation technique (abbreviated as STI) should be adopted instead. According to the STI technique, a thick oxide film is buried in a trench formed on a silicon surface, and thereafter the silicon surface is uniformly polished off, so that the oxide film is locally buried. If a topological difference is present on a substrate, a bottom of the topological difference is buried thereacross with the oxide film, and so that it should be concluded that the technique disclosed in the publication of Laid-Open Japanese patent application 63-266866 cannot be applied in this situation.